1. Field
Embodiments described herein relate to a method for implementing a circuit design for an integrated circuit, and a computer-readable medium.
2. Description of the Related Art
An FPGA (Field Programmable Gate Array) is a kind of integrated circuit in which a user can write a logical circuit of user's own to achieve operation desired by the user. An internal circuit in the FPGA can be rewritten even after it is shipped as a product. In order to implement wiring for connecting logical blocks placed in a related-art FPGA layout, a plurality of wires selected in advance are used for the wiring to make the wiring length among the logical blocks the shortest, that is, to make the operating frequency the highest. When the performance (operating frequency) requested by the user is satisfied, the wiring arranged thus is used. Otherwise, wiring is tried again from the step of selecting wires.
In the FPGA arranged and wired thus, there may be a large number of wires or logical blocks that are not used as a circuit, differently from an ASIC (Application Specific Integrated Circuit). A current flows into such a wire or a logical block though the wire or the logical block is not used. Thus, there is a problem that total power consumption (particularly, static power consumption) of the FPGA increases.    [Non-Patent Document 1] KARA K. W. POON, STEVEN J. E. Wilton, and Andy YAN, “A Detailed Power Model for Field-Programmable Gate Arrays”, ACM Trans. on Design Automation of Electronic Systems, Vol. 10, No 2, April 2005.    [Patent Document 1] U.S. Pat. No. 7,281,233